(1) Field of the Invention
This invention relates to a correlated double sampling circuit and a CMOS image sensor and, more particularly, to a correlated double sampling circuit for processing signals output from a pixel section where solid-state image sensing devices are arranged like a matrix and a CMOS image sensor including such a correlated double sampling circuit.
(2) Description of the Related Art
Solid-state image sensing devices used now for digital cameras, digital video cameras, and the like include image sensors using charge coupled devices (CCDs) and image sensors using complementary metal oxide semiconductor (CMOS) sensors. CMOS image sensors have merits. For example, CMOS image sensors consume a smaller amount of power than CCDs, CMOS image sensors can be driven by a single power source, and peripheral circuits, such as a timing generation circuit and read circuit, can be formed so that they will be one with CMOS image sensors. Therefore, CMOS image sensors have been used widely in recent years.
A CMOS image sensor comprises a pixel section where unit pixels including a photodiode are arranged like a matrix, a scanning circuit for scanning unit pixels in order, and a correlated double sampling (CDS) circuit for processing signals output from the pixel section.
This CDS circuit will now be described with reference to drawings. FIG. 5 is a circuit diagram of a unit pixel and CDS circuit.
A unit pixel 11 includes a photodiode D1, a reset transistor M1, a drive transistor M2, and a selection transistor M3. A plurality of unit pixels 11 each having the above structure are arranged like a matrix to form a pixel section. The pixel section is scanned in order by a vertical scanning shift register for scanning in a vertical direction and a horizontal scanning shift register for scanning in a horizontal direction.
There is a CDS circuit 60 for each column in the pixel section. The CDS circuit 60 processes a signal output from a unit pixel in a row selected by the vertical scanning shift register from among unit pixels in a column to which the CDS circuit 60 is connected. The CDS circuit 60 includes a first capacitor C1, a second capacitor C2, a power source VREF for generating reference potential Vref, amplifiers AMP1 and AMP2 for amplifying signals, a switch SW1, being a switching element, for controlling connection with the unit pixel 11, a switch SW2, being a switching element, for connecting one end of the second capacitor C2 to the first capacitor C1 and power source VREF, and a switch SW3, being a switching element, for outputting output signals to an output bus.
A current source I1 is located to make the transistor M2 in the unit pixel 11 function as an amplifier.
Now, the operation of the above unit pixel and CDS circuit will be described. FIG. 6 is a timing chart of a CDS circuit.
First, a selection signal SLCT1 for selecting pixels in the first row is turned to ON by the vertical scanning shift register (the selection signal SLCT1 changes to the H level). Then a reset signal RST1 for resetting pixels in the first row is kept “H” for a certain period of time to perform the first reset called an initial reset. At this time the potential on the cathode side of the photodiode D1 is VR (constant). After the reset time ended, the reset signal RST1 is turned to “L.” By doing so, the photodiode D1 begins integration according to the intensity of light. Then by turning the switch SW2 (it is assumed that there are eight columns of unit pixels and therefore switches SW2-1 through SW2-8) and switch SW1 in the CDS circuit 60 located for each column to ON, detected signals according to time during which the photodiode D1 integrates are accumulated as electric charges not only in the first capacitor C1 but also in the second capacitor C2. After a certain period of time elapsed, the switch SW1 and switches SW2-1 through SW2-8 are turned to OFF to hold the detected signals sampled. Subsequently, the reset signal RST1 is kept “H” for a certain period of time as the second reset and the switch SW1 is turned to ON during this time. By doing so, reset noise is accumulated in the first capacitor C1. After a predetermined period of time elapsed, the switch SW1 is turned to OFF. As a result, the potential at node VC2 of the second capacitor C2 is given by the following equation (1)Vref−((detected signal+reset noise)−reset noise)  (1)Therefore, only signal components can be extracted. After that the signals are transferred to the output bus line by turning the switch SW2 and switch SW3 in each CDS circuit (the switch SW2-1 and switch SW3-1, the switch SW2-2 and switch SW3-2, . . . , and the switch SW2-8 and switch SW3-8) to ON in synchronization with a scanning signal from the horizontal scanning shift register.
With conventional CDS circuits, however, a switching element for sampling detected signals is also used as a switching element for reading. Therefore, node potential on the reference voltage side, being reference, will shift at the time of the switch being turned to OFF, so that there will be differences in brightness among output images.
As described above, when detected signals according to time during which the photodiode D1 integrates are accumulated in the first capacitor C1 and second capacitor C2 as electric charges to sample the detected signals, the switches SW1 and SW2 in the CDS circuit 60 are turned to ON and are turned to OFF after a certain period of time. When the switch SW2 is turned to OFF, node potential on the reference voltage side, being reference, will shift by the influence of parasitic capacitance between the gate and source of a switching element, being the switch SW2, and between the gate and drain.
Moreover, there will be a shift in node potential caused by a layout. FIGS. 7A, B shows a schematic of a layout and changes in reference voltage. FIG. 7A is a schematic of a layout. FIG. 7B is a simple view showing changes in reference voltage corresponding to the switches SW2-1 through SW2-8.
In reference to FIG. 7A, the switch SW2 serving both as a switching element for sampling signals output from the unit pixel 11 and as a switching element for reading to the output bus is included in a CDS circuit located for each column. Switching elements 61 (SW2-1 through SW2-8, for example) are arranged in a row and are connected to a common reference voltage signal line 62. Each of the switching elements SW2-1 through SW2-8 is controlled by an SW2 switch on/off control circuit 63. When a control signal for common operation is input to the SW2 switch on/off control circuit 63, an on/off control signal generation section 64 corresponding to each switching element 61 generates a control signal. As a result, the switching elements SW2-1 through SW2-8 perform common operation. The switching elements SW2-1 through SW2-8 turn to ON/OFF in this way by a control signal for common operation, but in reality delays will occur. Therefore, when the SW2 turns to ON/OFF, reference voltage will fluctuate by the influence of the capacitance of a CDS circuit. If the SW2-1 through SW2-8 are turned to OFF in that order, a shift in reference voltage will gradually become great due to fluctuations in the reference voltage, the wiring resistance of the reference voltage signal line 62, and the like. It is assumed that a dashed line in FIG. 7B indicates ideal reference voltage (reference potential Vref). Then almost ideal reference voltage is obtained at the SW2-1, but reference voltage at the SW2-8 is lower than the ideal reference potential (Vref) by the influence of capacitance, wiring resistance, and the like. Such fluctuations in reference voltage will lead to a shift in the potential VC2 of a node on the reference voltage side. As a result, a shift in the number of electric charges accumulated in the second capacitor C2 will occur and differences in brightness will arise among results obtained when the CDS circuit 60 reads detected signals. It is assumed that pixels corresponding to the SW2-1 through SW2-8 output detected signals indicative of the same brightness. Then in the case of FIG. 7B, a pixel corresponding to the SW2-8 is duller than a pixel corresponding to the SW2-1. That is to say, a difference in brightness arises. A case where reference voltage at the SW2-8 is lower than the ideal reference potential (Vref) has been described. However, reference voltage at the SW2-8 may exceed the ideal reference potential (Vref), depending on how to control the switches. In this case, differences in brightness will also arise among the corresponding pixels.
Pixel sections have become minute, so the rate at which signals output from the pixel sections are read must be increased. Therefore, the width of a gate on the switching element SW2 used at read time must be widened to reduce its ON-state resistance. However, widening gate width will strengthen the influence of parasitic capacitance produced there and make a shift in the potential of a node on the reference voltage side great.
A shift in output signal caused by such a shift in the potential of a node on the reference voltage side is amplified by an amplifier located at the next stage of a CDS circuit. Therefore, even if a shift in signals output from a CDS circuit is small, differences in brightness will eventually arise among images. If an amplifier with an amplification factor of, for example, 16 is located at the next stage, a shift of 1 mV will be amplified to 16 mV.